Field of the Invention
The present invention relates to a method for producing a semiconductor device that includes surrounding gate MOS transistors (SGTs).
Description of the Related Art
Applications of surrounding gate MOS transistors (hereinafter referred to as SGTs) to semiconductor elements that offer highly integrated semiconductor devices have expanded in recent years and higher integration of SGT-including semiconductor devices is pursued under such trends.
FIG. 5 shows a structure of a representative example of a CMOS inverter circuit that includes MOS transistors. The CMOS inverter circuit includes an N-channel MOS transistor 100a and a P-channel MOS transistor 100b. A gate 101a of the N-channel MOS transistor 100a and a gate 101b of the P-channel MOS transistor 100b are connected to an input terminal Vi. A drain 102a of the N-channel MOS transistor 100a and a drain 102b of the P-channel MOS transistor 100b are connected to an output terminal Vo. A source 103b of the P-channel MOS transistor 100b is connected to a power source terminal VDD. A source 103a of the N-channel MOS transistor 100a is connected to a ground terminal VSS. In this CMOS inverter circuit, when an input voltage corresponding to “1” or “0” is applied to the input terminal Vi, an output voltage corresponding to the inverted input voltage, “0” or “1,” is output from the output terminal Vo.
These types of CMOS inverter circuits are used in many circuit chips such as microprocessors and the like. Increasing the degree of integration of CMOS inverter circuits directly leads to size-reduction of circuit chips such as microprocessors. Moreover, size reduction of circuit chips that use CMOS inverter circuits leads to cost reduction of circuit chips.
FIG. 6 is a cross-sectional view of a known planar CMOS inverter circuit. As illustrated in FIG. 6, an N-well region 105 (hereinafter a semiconductor region where a P-channel MOS transistor is formed and that contains a donor impurity is referred to as an N-well region) is formed in a P-type semiconductor substrate 104 (hereinafter a semiconductor substrate that contains an acceptor impurity is referred to as a P-type semiconductor substrate). Element isolation insulating layers 106a and 106b are each formed between a surface layer portion of the N-well region 105 and a surface layer portion of the P-type semiconductor substrate 104. A gate oxide film 107a for a P-channel MOS transistor and a gate oxide film 107b for an N-channel MOS transistor are respectively formed on a surface of the P-type semiconductor substrate 104 and a surface of the N-well region 105. A gate conductor layer 108a for a P-channel MOS transistor and a gate conductor layer 108b for an N-channel MOS transistor are respectively formed on the gate oxide film 107a and the gate oxide film 107b. On the left side of the gate conductor layer 108a for a P-channel MOS transistor, a P+ region 109a (a semiconductor region that has a high acceptor impurity concentration is hereinafter referred to as a “ P+ region”) is formed on a surface of the N-well region 105. On the right side of the gate conductor layer 108a, a P+ region 109b is formed on the surface of the N-well region 105. Similarly, a N+ region 110b (a semiconductor region having a high donor impurity concentration is hereinafter referred to as an “N+ region”) is formed on the surface of the P-type semiconductor substrate 104 on the right side of the gate conductor layer 108b for a N-channel MOS transistor, and a N+ region 110a is formed on the surface of the P-type semiconductor substrate 104 on the left side of the gate conductor layer 108b. A first interlayer insulating layer 111 is formed. Contact holes 112a, 112b, 112c, and 112d are formed in the first interlayer insulating layer 111 so as to be on the P+ regions 109a and 109b and the N+ regions 110a and 110b, respectively.
A power supply wiring metal layer Vdd formed on the first interlayer insulating layer 111 is connected to the P+ region 109a of the P-type MOS transistor through the contact hole 112a. An output wiring metal layer Vo formed on the first interlayer insulating layer 111 is connected to the P+ region 109b of a P− channel MOS transistor and the N+ region 110a of an N-channel MOS transistor through the contact holes 112b and 112c. A ground wiring metal layer Vss is connected to the N+ region 110b of an N-channel MOS transistor through the contact hole 112d. A second interlayer insulating layer 113 is formed on the first interlayer insulating layer 111. Contact holes 114a and 114b are formed so as to penetrate through the first interlayer insulating layer 111 and the second interlayer insulating layer 113. The contact hole 114a is on the gate conductor layer 108a for a P-channel MOS transistor and the contact hole 114b is on the gate conductor layer 108b for a N-channel MOS transistor. An input wiring metal layer Vi formed on the second interlayer insulating layer 113 is connected to the gate conductor layer 108a for a P-channel MOS transistor and the gate conductor layer 108b for an N-channel MOS transistor through the contact holes 114a and 114b. 
In order to reduce the area in which a planar CMOS inverter circuit is formed, it is necessary to reduce the two-dimensional size of the P-type semiconductor substrate 104, on which the gate conductor layers 108a and 108b of P- and N-channel MOS transistors, the N+ regions 110a and 110b, the P+ regions 109a and 109b, the contact holes 112a, 112b, 112c, 112d, 114a, and 114b, and the wiring metal layers 108a and 108b are formed, as viewed in plan in a direction perpendicular to the substrate surface. In a typical planar CMOS inverter circuit, many contact holes are formed in addition to the contact holes 112a, 112b, 112c, 112d, 114a, and 114b. Accordingly, in order to form fine contact holes at high accuracy, processing technologies such as lithographic technologies and etching technologies are required to achieve ever higher accuracy.
In a typical planar MOS transistor, the channel of a P- or N-channel MOS transistor lies in a horizontal direction along the surface of the P-type semiconductor substrate 104 and the N-well region 105 and between the source and the drain. In contrast, the channel of an SGT lies in a direction perpendicular to a surface of a semiconductor substrate (for example, refer to Japanese Unexamined Patent Application Publication No. 2-188966, and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)).
FIG. 7A is a schematic diagram illustrating an N-channel SGT. N+ regions 116a and 116b are respectively formed in a lower portion and an upper portion of a P-type or i-type (intrinsic) Si pillar 115 (hereinafter a silicon semiconductor pillar is referred to as a Si pillar). When one of the N+ regions 116a and 116b functions as a source, the other functions as a drain. A portion of the Si pillar 115 that lies between the source and drain N+ regions 116a and 116b is a channel region 117. A gate insulating layer 118 is surrounds the channel region 117, and a gate conductor layer 119 surrounds the gate insulating layer 118. In a SGT, source and drain N+ regions 116a and 116b, the channel region 117, the gate insulating layer 118, and the gate conductor layer 119 are formed in one Si pillar 115. Thus, the area of the surface of the SGT appears to be equal to the area of one source or drain N+ region of a planar MOS transistor. Accordingly, a circuit chip that includes SGTs can achieve further chip-size reduction compared to a circuit chip that includes planar MOS transistors.
FIG. 7B is a cross-sectional view of an SGT-including CMOS inverter circuit (for example, refer to Japanese Unexamined Patent Application Publication No. 7-99311).
As illustrated in FIG. 7B, an i-layer 121 (“i-layer” refers to an intrinsic Si layer) is formed on an insulating layer substrate 120 and a Si pillar SP1 for a P-channel SGT and a Si pillar SP2 for an N-channel SGT are formed on the i-layer 121.
The i-layer 121 is connected to a lower portion of the Si pillar SP1 of a P-channel SGT. A P+ region 122 of a P-channel SGT is formed in the same layer as the i-layer 121 and surrounds the lower portion of the Si pillar SP1. A N+ region 123 of an N-channel SGT is formed in the same layer as the i-layer 121 and surrounds the lower portion of the Si pillar SP2.
A P+ region 124 of a P-channel SGT is formed in an upper portion of the Si pillar SP1 for a P-channel SGT. A N+ region 125 of an N-channel SGT is formed in an upper portion of the Si pillar SP2 for an N-channel SGT.
As illustrated in FIG. 7B, gate insulating layers 126a and 126b are formed so as to surround the Si pillars SP1 and SP2. A gate conductor layer 127a of a P-channel SGT and a gate conductor layer 127b of an N-channel SGT are formed so as to surround the gate insulating layers 126a and 126b. 
Insulating layers 128a and 128b are formed so as to surround the gate conductor layers 127a and 127b. 
The P+ region 122 of a P-channel SGT and the N+ region 123 of an N-channel SGT are connected to each other through a silicide layer 129b. A silicide layer 129a is formed on the P+ region 124 of a P-channel SGT and a silicide layer 129c is formed on the N+ region 125 of an N-channel SGT. An i-layer 130a between the P+ region 122 under the Si pillar SP1 and the P+ region 124 in an upper portion of the Si pillar SP1 serves as a channel of a P-channel SGT. An i-layer 130b between the N+ region 123 under the Si pillar SP2 and the N+ region 125 in an upper portion of the Si pillar SP2 serves as a channel of an N-channel SGT.
As illustrated in FIG. 7B, a SiO2 layer 131 is formed by chemical vapor deposition (CVD) so as to cover the i-layer substrate 120 (insulating layer substrate) and the Si pillars SP1 and SP2. Contact holes 132a, 132b, and 132c are formed in the SiO2 layer 131. The contact hole 132a is formed on the Si pillar SP1, the contact hole 132c is formed on the Si pillar SP2, and the contact hole 132b is formed on part of the P+ region 122 and the N+ region 123.
A power supply wiring metal layer Vdd on the SiO2 layer 131 is connected to the P+ region 124 of a P-channel SGT and the silicide layer 129a through the contact hole 132a. An output wiring metal layer Vo on the SiO2 layer 131 is connected to the P+ region 122 of a P-channel SGT, the N+ region 123 of an N-channel SGT, and the silicide layer 129b through the contact hole 132b. The ground wiring metal layer Vss on the SiO2 layer 131 is connected to the N+ region 125 of an N-channel SGT and the silicide layer 129c through the contact hole 132c. 
The gate conductor layer 127a of a P-channel SGT and the gate conductor layer 127b of an N-channel SGT are connected to each other and to an input wiring metal layer (not shown in the drawing). Since a P-channel SGT and an N-channel SGT are respectively formed in the Si pillar SP1 and the Si pillar SP2 in the inverter circuit that has these SGTs, the area of the circuit in a plan view taken in a direction perpendicular to the insulating layer substrate 120 is reduced. Accordingly, the circuit can achieve further side reduction compared to an inverter circuit that has typical planar MOS transistors.
Currently, efforts are being made to further reduce the size of a circuit chip that includes SGTs. In this regard, as illustrated in the diagram of FIG. 8, it has been predicted that the circuit area can be reduced by respectively forming two SGTs in an upper portion and a lower portion of one Si pillar SPa (for example, refer to Hyoungiun Na and Tetsuo Endoh: “A New Compact SRAM cell by Vertical MOSFET for Low-power and Stable Operation”, Memory Workshop, 201 3rd IEEE International Digest, pp. 1 to 4 (2011)).
As illustrated in FIG. 8, a CMOS inverter circuit includes an N-channel SGT 133a formed in a lower portion of the Si pillar SPa and a P-channel SGT 133b is formed above the N-channel SGT 133a. A N+ region 134a of the N-channel SGT 133a is formed in a lower portion of the Si pillar SPa, and is connected to the ground wiring metal layer Vss. A channel i-layer 136a is formed on the N+ region 134a. A gate insulating layer 137a is formed on the outer periphery of the channel i-layer 136a. A gate conductor layer 138a for an N-channel SGT is formed on the outer periphery of the gate insulating layer 137a. A N+ region 134b is formed on the channel i-layer 136a. A P+ region 135a of the P-channel SGT 133b is formed on the N+ region 134b. A channel i-layer 136b is formed on the P+ region 135a. A gate insulating layer 137b is formed on the outer periphery of the channel i-layer 136b, and a gate conductor layer 138b for the P-channel SGT 133b is formed on the outer periphery of the gate insulating layer 137b. A P+ region 135b is formed in a top portion of the Si pillar SPa and on the channel i-layer 136b. The P+ region 135b is connected to the power supply wiring metal layer VDD. A connecting part 160a that is in contact with the gate conductor layer 138a of the N-channel SGT 133a and is formed of a metal wire having an opening and a connecting part 160b that is in contact with the gate conductor layer 138b of the P-channel SGT 133b and is formed of a metal wire having an opening are connected to the input wiring metal layer Vi. A connecting part 161 formed of a metal wire and having an opening in contact with the N+ region 134b of the N-channel SGT 133a and the P+ region 135a of the P-channel SGT 133b (this opening corresponds to the contact hole 132b on the P+ region 122 and the N+ region 123 in FIG. 7B) is connected to an output terminal wire Vo.
Some production difficulties need to be resolved in order to form an SGT-including inverter circuit in one Si pillar SPa as illustrated in FIG. 8. That is, in FIG. 8, the P+ region 135a of the P-channel SGT 133b and the N+ region 134b of the N-channel SGT 133a that lie in a middle portion of the Si pillar SPa are in contact with each other. Thus, the connecting part 161 that is in contact with the N+ region 134b of the N-channel SGT 133a and the P+ region 135a of the P-channel SGT 133b must be formed on the side wall of the Si pillar SPa. This means that the opening of the connecting part 161 must be formed on the side wall of the Si pillar SPa. Similarly, the openings of the connecting parts 160a and 160b in contact with the gate conductor layers 138a and 138b must also be formed on the side wall of the Si pillar SPa. This means that fine openings of the connecting parts 160a, 160b, and 161 each formed of a metal wire having an opening must be formed on the side wall of the Si pillar SPa with high accuracy. Although it is necessary to highly accurately form fine openings on the side wall of the Si pillar SPa in order to form openings of the connecting parts 160a, 160b, and 161, this cannot be achieved by a known method for forming fine contact holes 112a, 112b, 112c, 112d, 114a, 114b, 132a, 132b, and 132c with high accuracy in a flat region on the semiconductor substrate 104 and the insulating layer substrate 120 described by referring to FIGS. 6 and 7B.
FIG. 9 is a diagram showing a structure that includes two Si pillars, SPb and SPc, two SGTs, namely, SGT139a and SGT 139b, formed in the Si pillar SPb, and two SGTs, namely, SGT 140a and 140b, formed in the Si pillar SPc with the SGTs 139a, 139b, 140a, and 140b being connected to one another through a conducting wire. The SGT 139a formed in a lower portion of the Si pillar SPb is constituted by source and drain N+ regions 141a and 141b, a channel i-region 150a, a gate insulating layer 143a, and a gate conductor layer 144a. The SGT 139b in the upper portion of the Si pillar SPb is constituted by P+ regions 142a and 142b, a channel i-region 150b, a gate insulating layer 143b, and a gate conductor layer 144b. The SGT 140a in the lower portion of the Si pillar SPc is constituted by N+ regions 145a and 145b, a channel i-region 151a, a gate insulating layer 147a, and a gate conductor layer 148a. The SGT 140b in the upper portion of the Si pillar SPc is constituted by N+ regions 146a and 146b, a channel i-region 151b, a gate insulating layer 147b, and a gate conductor layer 148b. 
As illustrated in FIG. 9, a connecting part 163a that is formed of a metal wire having an opening, the metal wire contacting the gate conductor layer 144a and surrounding the Si pillar SPb, is formed. A connecting part 163b that is formed of a metal wire having an opening, the metal wire contacting the gate conductor layer 144b and surrounding the Si pillar SPb, is formed. A connecting part 149a that is formed of a metal wire having an opening, the metal wire contacting the gate conductor layer 148a and surrounding the Si pillar SPc, is formed. A connecting part 149b that is formed of a metal wire having an opening, the metal wire contacting the gate conductor layer 148a and surrounding the Si pillar SPc, is formed. A connecting part 164a that is formed of a metal wire having an opening, the metal wire contacting the N+ region 141b and the P+ region 142a and surrounding the Si pillar SPb, is formed. A connecting part 164b that is formed of a metal wire having an opening, the metal wire contacting the N+ region 145b and the N+ region 146a, is formed.
As illustrated in FIG. 9, in the Si pillar SPb, the connecting part 163a is connected to a metal terminal wiring V1, the connecting part 163b is connected to a metal terminal wiring V2, and the connecting part 164a is connected to a metal terminal wiring V4. In the Si pillar SPc, the connecting part 149a is connected to a metal wiring 162a, the connecting part 149b is connected to a metal terminal wiring V3, and the connecting part 164b is connected to a metal wiring 162b. The connecting part 163a and the connecting part 149a are connected to each other via the metal wiring 162a and the connecting part 164a and the connecting part 164b are connected to each other via the metal wiring 162b. 
In forming an SGT-including inverter circuit illustrated in FIG. 9, it is preferable to form the connecting part 163a and the connecting part 149a simultaneously at the same position in terms of the height in a perpendicular direction (height direction) of the Si pillars SPb and SPc. As a result, the number of steps required to form the connecting parts 163a and 149a can be reduced. Similarly, it is preferable to form the connecting part 163b and the connecting part 149b simultaneously at the same position in terms of the height in the perpendicular direction of the Si pillars SPb and SPc. The connecting part 164a and the connecting part 164b are preferably formed simultaneously at the same position in terms of height in the perpendicular direction of the Si pillars SPb and SPc. In order to achieve this, the openings of the connecting part 163a and the connecting part 149a must be formed simultaneously at the same height in the perpendicular direction of the Si pillars SPb and SPc and the same applies to the openings of the connecting part 163b and the connecting part 149b and the openings of the connecting part 164a and the connecting part 164b. Furthermore, the openings of these connecting parts 163a, 163b, 149a, 149b, 164a, and 164b must be fine and made highly accurately. Although it is necessary to highly accurately form fine openings on the side walls of the Si pillars SPb and SPc to form these openings, this cannot be achieved by a known method for forming fine contact holes 112a, 112b, 112c, 112d, 114a, 114b, 132a, 132b, and 132c with high accuracy in a flat region on the semiconductor substrate 104 and the insulating layer substrate 120 described by referring to FIGS. 6 and 7B.
As illustrated in FIG. 10, a gate insulating layer 152 that surrounds the Si pillar SPb is formed as one continuous layer that bridges the SGT 139a and the SGT 139b in the upper and lower portions of the Si pillar SPb. A gate conductor layer 153 is also formed as one continuous layer. A connecting part 154 and a metal terminal wiring V5 are formed to be in contact with the gate conductor layer 153. A connecting part 155 that is in contact with the N+ region 141b and the P+ region 142a and is connected to the connecting part 164b via the metal wiring 162b is formed so as not to electrical short with the gate conductor layer 153. According to this approach illustrated in FIG. 10, the gates of the SGT 139a and the SGT 139b in the upper and lower portions of the Si pillar SPb can be electrically connected to each other via the gate conductor layer 153, the connecting part 154, and the metal terminal wiring V5 whereas the structure illustrated in FIG. 9 requires two connecting parts 145a and 145b and two metal terminal wirings V1 and V2 in order to electrically connect the gate conductor layers 144a and 144b of the SGT 139a and the SGT 139b in the upper and lower portions of the Si pillar SPb to each other. In order to form the structure illustrated in FIG. 10, it is necessary to form the opening of the connecting part 155 so as not to be in contact with the gate conductor layer 153. Forming this opening requires highly accurate forming of a fine opening in the side wall of the Si pillar SPb. However, this cannot be achieved by a known method for forming fine contact holes 112a, 112b, 112c, 112d, 114a, 114b, 132a, 132b, and 132c with high accuracy in a flat region on the semiconductor substrate 104 and the insulating layer substrate 120 described by referring to FIGS. 6 and 7B.
According to the methods for producing SGT-including semiconductor devices described by referring to FIGS. 8, 9, and 10, SGTs are formed on top of the other in each of the Si pillars SPa, SPb, and SPc in a longitudinal direction and Si pillars SPa, SPb, and SPc are formed in which the N-channel SGTs 133a, 139a, 140a, and 140b, and P-channel SGTs 133b and 139b positioned in upper and lower portions of the Si pillars SPa, SPb, and SPc are used in different combinations. According to these production methods, it is difficult to form openings of the connecting parts 161, 164a, 164b, and 155 in contact with the N+ regions 134b, 141b, 145b, and 146a and the P+ regions 135a and 142a that contain donor or acceptor impurities and openings of the connecting parts 163a, 163b, 149a, 149b, and 154 of the gate conductor layers 138a, 138b, 145a, 145b, 149a, 149b, and 153 at predetermined positions with high accuracy.